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Manager, ASIC Design
at Meta
10 months ago | 1098 views | 2 applications

Manager, ASIC Design

Per year
$202,000 To $273,000

About the company

Meta builds technologies that help people connect, find communities and grow businesses. We’re building social experiences that keep your account secure and give you the power to make choices around how your data is used.

Job Summary


📍Manage an ASIC front end design team responsible for AI/ML accelerators for Data centers. Drive Design planning, microarchitecture development and design execution 📍Review micro-architecture and design to meet architecture spec and optimize Power, 📍Performance and Area. Drive key metrics and milestones to meet silicon tape out schedule 📍Partner with Architecture, SW/FW, Design Verification, Modeling, Emulation, and Post-Silicon Validation teams to achieve high quality design 📍Partner with internal and external cross-functional teams, across all levels of a corporation, from executives, team managers and individual contributors including development engineers, capacity planners and supply chain experts 📍Contribute to and drive development of and maintain overall silicon strategy aligned to corporation's Long Range Plan objectives 📍Identify candidates, hire, schedule, support and train a team of ASIC engineers in order to develop products on time and on budget 📍Contribute to, analyze, review SOWs from vendors, supporting documentation, requirements sets that meet the needs of internal customers 📍Support engineering teams to define, debug, implement and deliver total solutions around purpose built ASICs 📍Define, implement and maintain key performance indicators (KPI) for areas of responsibility 📍Partner with technical program management and supply chain team members to manage external development partners, suppliers and vendors

Minimum Qualifications

📍B.S. or M.S. degree in Computer Engineering or Electrical Engineering 📍10+ years experience managing ASIC/SoC design teams at the Director or Manager level and working across multiple projects and adjusting priorities in partnership with stakeholders 📍Experience with multiple successful ASIC tape outs. Track record of first-pass success 📍Experienced with interpreting functional specs and developing architecture, microarchitecture and logic design. Experience working with Synthesis, timing and design constraints 📍Experience with SOC bring-up and post silicon validation, gate level testing and multi clock design practices (CDC) 📍Clear understanding of state-of-the-art design flows, design and verification methodologies 📍Knowledge of neural networks and machine learning concepts, and/or other neural network development framework

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