About the company
Block is one company built from many blocks, all united by the same purpose of economic empowerment. The blocks that form our foundational teams — People, Finance, Counsel, Hardware, Information Security, Platform Infrastructure Engineering, and more — provide support and guidance at the corporate level. They work across business groups and around the globe, spanning time zones and disciplines to develop inclusive People policies, forecast finances, give legal counsel, safeguard systems, nurture new initiatives, and more. Every challenge creates possibilities, and we need different perspectives to see them all. Bring yours to Block.
Job Summary
You Will:
📍Perform block level P&R, and integration from early RTL to final tapeout 📍Work closely with logic designers on block level timing closure 📍Work closely with custom cell development 📍Improve capacity and scalability of our full chip design flows 📍Develop scripts to enhance current physical design infrastructure/methodology 📍Collaborate with teammates from different functions and time zones
You Have:
📍10+ years of relevant experience with BSEE or Applied Science degree; 8+ years in combination with a MS degree 📍Expert in using Synopsys ICC2/Fusion Compiler and PrimeTime 📍Understanding of the full design cycle from RTL to GDSII, including chip level 📍Prior experience with custom physical design and relative placement 📍Successfully tapped out multiple chips in 5nm and below 📍Experience with all aspects of block delivery including clock, power analysis, physical verification, etc.
